Wafers utilizing Semiconductor-On-Insulator (SOI) technology are generally composite structures consisting of an active layer of silicon deposited on insulating materials. The insulator, or dielectric, can be sapphire, silicon dioxide, silicon nitride, or other insulating form of silicon. Composition of a SOI wafer prior to processing typically consists of a stack as illustrated in FIG. 1, which illustrates a cross-sectional view of a portion 100 of a SOI wafer with a top silicon layer 16 for fabricating a fully depleted SOI technology semiconductor device. Portion 100 includes a lower or support substrate 12, a buried insulative layer 14, as well as thin top silicon layer 16. Insulative layer 14 is generally a buried oxide (BOX) layer that serves as an insulating layer between the support substrate 12 and the top silicon layer 16. Depending upon the processing technology and device requirements, the thickness of the upper or top silicon layer 16 may vary between 5 and 200 nm or more. The portion 100 shown in FIG. 1 serves as the basis or foundation needed to begin the device fabrication procedures or process flow, e.g., series of photolithography and etch processes for alignment mark formation, STI formation, back side contact formation, and the like.
In the manufacture of devices employing SOI technology, formation of alignment marks is typically the first step. Formation of alignment marks is necessary because in subsequent lithography operations, e.g., shallow trench isolation (STI) feature formation, the wafer must be positioned such that the pattern exposed into the photo resist from previous lithography operations aligns properly. If the SOI top layer silicon 16 is significantly thinner than the required, or optimum, alignment mark depth, e.g., 10 nm top silicon layer thickness and 120 nm optimum depth for step/scan contrast, it is not possible to use alignment marks formed only in the top silicon layer 16, or in the insulative layer 14, as insufficient contrast for the pattern alignment process would exist. For this reason, the alignment marks must be formed in the lower substrate silicon 12. Alignment marks are formed by an exposure, without alignment, followed by an etch process, which transfers the resist pattern into the wafer silicon substrate 12. The alignment marks formed in the substrate 12 have an optimal depth D (seen in FIG. 13), dependant upon specific pattern alignment equipment, to provide a desired level of contrast for the optical pattern alignment system. For example, step and scan alignment systems manufactured by ASML have an optimum depth of about 120 nm, while systems manufactured by others, e.g., Canon, Nikon, etc., have a different optimum depth.
The conventional alignment mark formation process requires two lithography and etch steps, as discussed with reference to FIGS. 2 and 3. Following alignment mark formation, an STI pattern is transferred into the top silicon layer 16 through a third lithography and etch step, as presented with reference to FIGS. 4 and 5.
FIG. 2 illustrates a cross-sectional view of the portion 100 of the SOI wafer of FIG. 1 after thermal growth of pad oxide layer 15, nitride layer 17 deposition, and the first photolithography masking and etch of the nitride/oxide/silicon/oxide stack to form location or window 5 for later alignment feature patterns. In addition, the photo resist mask has been removed from portion 100 in FIG. 2. This first photolithography and etch step uncovers the upper surface of substrate silicon 12 and forms the window location 5. Portion 100 will then be masked with the alignment pattern, and an etch into the lower or support substrate 12 will be conducted, with the result illustrated in FIG. 3.
FIG. 3 illustrates portion 100 of FIG. 2 after the second lithography and etch step and removal of the second photo resist mask. The second mask is used to image or pattern the location of alignment features 7 where window 5 had been formed in the first etch step. An etch to form the alignment features 7 is conducted into the lower or support substrate 12 to a desired depth, e.g., the desired, or predefined, depth for proper stepper/scanner contrast. With the creation of alignment features 7, portion 100 can now undergo a third mask and etch step to form shallow trench isolation feature patterns, as seen in FIG. 4.
FIG. 4 illustrates portion 100 of FIG. 3 after the third lithography and etch step, and removal of the photo resist mask. Shallow trench patterns are masked, utilizing the alignment features 7 for alignment to assure proper positioning, and then openings 9 are etched through nitride layer 17, pad oxide layer 15, and top silicon layer 16 to form STI trenches. During the STI etch, the photo resist defining the location of openings 9 (not shown) protects the alignment features 7. Etch of openings 9 is stopped upon reaching the buried oxide layer 14. Portion 100 is ready to undergo trench fill and planarization, as shown in FIG. 5.
FIG. 5 illustrates portion 100 of FIG. 4 after trench fill, planarization, and removal of nitride layer 17 and pad oxide layer 15. Silicon oxide 8 is used to fill the trench openings 9, as well as to cover the alignment features 110. The silicon oxide fill 8 is then planarized, i.e., undergoes chemical mechanical polishing, and removal of nitride layer 17 and pad oxide layer 15 is accomplished. The portion 100 illustrated in FIG. 5 has, thus far, undergone three separate lithography and etch steps of the process flow in order to pattern alignment features 110 into substrate 12 and create STI features 10 in the thin top silicon layer 16.
In addition to the formation of alignment marks and STI features, in SOI technology it is customary to form some electrical contacts to the “back side” of the wafer, i.e., to the substrate 12 beneath the insulating buried oxide layer 14. This is required to ensure that the potential at the top silicon/buried oxide interface is kept at a constant value instead of being allowed to “float.” To obtain good ohmic contact, the contacted substrate area must undergo a silicidation process. In conventional processing, a window for the back-side contact is etched through the trench isolation and barrier oxides before silicide formation, which is normally done for the source/drain and gate regions. FIGS. 6 and 7 detail the SOI process flow sequence for forming the back-side contact window, which adds an additional lithography and etch step to the SOI process flow illustrated in FIGS. 2 through 5.
Referring now to FIG. 6, which illustrates a cross-sectional view of a portion 200 of a SOI wafer which has undergone the first, second, and third lithography and etch steps of the process flow such as presented with reference to FIGS. 2 through 5, to form STI features in top silicon layer 26 and alignment features in substrate 22. A photo resist mask 20 is applied over portion 200 to form an opening 21 which will serve as the back-side contact window after etch through buried oxide 24, as seen in FIG. 7. It should be noted that gate structures and implants for source/drain regions are not depicted in FIG. 6 (or FIG. 7) in order to keep portion 200 straightforward and uncluttered.
FIG. 7 illustrates the portion 200 of FIG. 6 after the lithography and etch steps and resist removal. The etch creates a back-side window 25. Back-side window 25 extends through buried oxide 24 to substrate 12, and serves as the location at which the back-side contact will be formed in subsequent processing, i.e., silicidation.
To reach the point in the SOI process flow represented by FIG. 7 has required four lithography and etch processes, as discussed with reference to FIGS. 2 through 7. Thus when a thin silicon upper layer is used, considerably more manufacturing capacity and cycle time is required than that of processing of SOI with a medium SOI top layer thickness, where two lithography and etch steps are required. The thin SOI upper layer case also requires more manufacturing capacity and cycle time than the case of thick top layer or bulk material, in which three and two lithography and etch steps are needed respectively. However, in terms of device performance, it is desirable to use thin SOI top layers, as thin SOI top layers enable formation of fully depleted SOI devices, e.g., devices that have lower leakage currents.
A method to reduce the number of lithography and etch steps needed to form alignment marks, STI patterns, and back-side contact windows in SOI wafers would be useful and could reduce manufacturing cycle time while increasing manufacturing capacity.